Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - DDS Verilog

Search list

[Other resource] DDSFPGA_cylone

Description: dds设计，花了一个星期做的,verilog写的，可生成多种波形，频率范围可上M,性能不错。-dds design, spent a week doing, verilog written, multiple waveform generation, frequency range available on the M, good performance.
Platform: | Size: 637936 | Author: 苏纳 | Hits:

[Other resource] oneperiod

Description: 将正弦波分割，数字化处理，即dds技术，为verilog做准备
Platform: | Size: 3142 | Author: 严新文 | Hits:

[Other resource] dds_quicklogic

Description: 这是quicklogic公司的直接频率合成（DDS）Verilog代码
Platform: | Size: 22732 | Author: jinzhoulang | Hits:

[Other resource] DDSverilogsource

Description: DDS的VERILOG原代码，请大家多支持
Platform: | Size: 3305 | Author: 屈开 | Hits:

[Other resource] dds_using_FPGA

Description: verilog编写基于fpga的DDS实现
Platform: | Size: 448910 | Author: 宇天 | Hits:

[Other resource] code_for_wireless_communication

Description: 包含软件无线电、dds、滤波器设计、数字调制解调等常用无线通信设计的matlab\\verilog源码
Platform: | Size: 198113 | Author: 李大鹏 | Hits:

[Other resource] dds_drive.c

Description: DDS发生器NIOS .c文件,在NIOSII中可以配合Verilog代码生成的自定义外设产生DDS信号
Platform: | Size: 3973 | Author: 白天 | Hits:

[SourceCode] 四相载波发生器

Description: 本代码采用Altera公司的FPGA为主控芯片，以开发软件QuartusⅡ为工具，采用EDA设计中的自顶向下与层次式设计方法，使用精简的DDS算法完成了输入为14MHz，输出四路频率为70MHz的四相序正弦载波（相位分别为0°、90°、180°、270°）的设计。还完成了输入为14MHz，输出为70MHz的四相序方波载波（相位分别为0°、90°、180°、270°）的设计。利用Verilog HDL语言进行了程序设计并用QuartusⅡ对设计进行了仿真，验证了其正确性。
Platform: | Size: 5276 | Author: biyuming@mails.guet.edu.cn | Hits:

[VHDL-FPGA-Verilog] 用modelsim仿真一个正弦波产生程序

Description: 用modelsim仿真一个正弦波产生程序-modelsim simulation using a sine wave generated procedures
Platform: | Size: 68608 | Author: 阿乐 | Hits:

[Special Effects] yuv2rgb

Description:
Platform: | Size: 1024 | Author: scounix | Hits:

[VHDL-FPGA-Verilog] EDA_project

Description: 基于Verilog和VHDL的DDS程序 基于VHDL的8位十进制频率计 -Verilog and VHDL based on the DDS process VHDL-based 8-bit decimal Cymometer
Platform: | Size: 2381824 | Author: 李建兵 | Hits:

[SCM] DDS_VERILOG

Description: 超级精简的DDS发生器，用VERILOG编写，请参考-Super-streamlined DDS generator with VERILOG preparation, please refer to
Platform: | Size: 3072 | Author: 吴宏伟 | Hits:

[SCM] dds_var

Description: 自己写的一个简单的DDS控制器，此程序包包含完整的VERILOG写的程序，操作有点简单，输出正弦波，方波，锯齿波，通过键盘可以选择输出波形，与大家共享-To write a simple DDS controller, this package contains a complete program written in VERILOG, a bit simple to operate, the output sine wave, square wave, sawtooth, through the keyboard can select output waveform, and for all to share
Platform: | Size: 1184768 | Author: deng | Hits:

[VHDL-FPGA-Verilog] dds_mine

Description: 这是基于verilog的dds系统设计，比较简单，希望对大家有用-This is based on verilog for dds system design, relatively simple, hope for all of us! ! !
Platform: | Size: 488448 | Author: 林海 | Hits:

[Other] AD9851_VERILOG

Description: 一个DDS芯片AD9851的VERILOG程序，加74HC574锁存器！-A DDS chip AD9851' s VERILOG program, plus 74HC574 latch!
Platform: | Size: 1024 | Author: 陈枫 | Hits:

[Embeded-SCM Develop] new_128HZ

Description: 直接数字频率合成器DDS设计，VERILOG实现的，比较好的哦-DDS direct digital frequency synthesizer design, VERILOG implementation, and better oh
Platform: | Size: 965632 | Author: 洪依 | Hits:

[VHDL-FPGA-Verilog] DDS_verilog

Description: 通讯中常用的dds模块的verilog源码打包下载-Communications commonly used in dds module verilog source code package to download
Platform: | Size: 609280 | Author: sofia | Hits:

[VHDL-FPGA-Verilog] ex_DDS

Description: 基于Verilog语言实现DDS（数字频率合成器）的设计，有完整的工程设计代码和仿真脚本(Verilog language based on DDS (digital frequency synthesizer) design, there is a complete engineering design code and simulation scripts)
Platform: | Size: 7505920 | Author: WaaDee | Hits:

[VHDL-FPGA-Verilog] signal

Description: 简易频谱仪 256位 采用了直接数字频率合成技术(DDS)和计算机控制技术，选择美国Analog Devices公司的高度集成DDS芯片AD9851和AT89S52单片机作为控制器件，设计了一种基于DDS的程控信号发生器。用C语言进行了软件应用设计。实验结果表明，该信号发生器能较好地产生较高稳定度的激励信号，具有较高的实用价值。(Simple spectrum meter 256 bit)
Platform: | Size: 7323648 | Author: luke28 | Hits:

[VHDL-FPGA-Verilog] verilog实现dds

Description: 基于FPGA实现信号发生器的的功能，较好的参考资料。(The function of signal generator is realized based on FPGA, which is a good reference.)
Platform: | Size: 2594816 | Author: sudochang | Hits:
« 1 2 ... 4 5 6 7 8 910 11 12 13 »

CodeBus www.codebus.net